🔆 Overview

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If you have taken the following courses already, then please do not enroll for this course. The material of these courses overlap significantly. So, you will not learn much new stuff.

• Prof. Jeff Zhang's course titled "CEN/EEE 598: Advanced Hardware and Systems for Machine Learning"
• Prof. Aviral Shrivastava's course titled "CEN/CSE 598: Machine Learning Accelerator Design"

There is also quite a bit of overlap of this course with the following course. So, please look through the contents carefully to decide if you'd like this take this course.

• Prof. Jiaqi Zu's course titled "EEE 598: Algorithm/Hardware Co-Design and Design Automation for Emerging AI Hrdware" </aside>

👨‍🏫 Personnel

Instructor

Teaching Assistant

🎯 Course Description

Machine learning (ML) has become ubiquitous and is currently a dominant computing workload. This course covers design of hardware and software for training and inference in ML systems. Hardware choices for machine learning include CPUs, GPUs, FPGAs, and ASICs. Tradeoffs in implementing training and inference workloads using these different compute paradigms will be explored. Emerging ML accelerators will be studied. Students will read research papers, present their learnings in class, and complete a project.

Course Objectives

• Review of computer architecture and arithmetic
• Review of ML and Deep Learning (DL) networks
• Computing needs for ML/DL (Characterization of ML/DL workloads), including compute and memory demands for both training and inference
• Overview of acceleration architectures for ML
• Hardware-software co-design and design space exploration of accelerators
• Performance analysis and benchmarking of ML/DL workloads
• Optimization methods for improving the efficiency of ML/DL workloads
• Compilation/mapping of ML/DL workloads